منابع مشابه
PARALLEL SWITCH-LEVEL SIMULATION of VLSI CIRCUITS
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Parallel Logic Simulation of Digital Circuits By Hong Kyu Kim Parallel discrete event simulation (PDES) is e cient in simulating a large digital circuit. In this dissertation, two techniques are proposed to improve the performance of PDES in logic simulation. One is a partitioning algorithm and the other is a hybrid parallel simulation protocol. Experiments were performed to demonstrate that th...
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15 صفحه اولReducing Communication Overhead in Distributed Logic Simulation of Vlsi Circuits
Distributed simulation represents an attractive and smart way of improving the verification speed of large VLSI circuits. Unfortunately, this inexpensive approach suffers from the low performance of the communication networks used to connect local workstations. In this paper, we present a partitioning algorithm that attempt to find a suitable balance between the communication and the execution ...
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ژورنال
عنوان ژورنال: ACM Computing Surveys
سال: 1994
ISSN: 0360-0300,1557-7341
DOI: 10.1145/185403.185424